1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for updating control state variables of a process control model based on rework data.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Generally, a set of processing steps is performed on a lot of wafers using a variety of processing tools, including photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, implantation tools, etc. Semiconductor devices are manufactured from wafers of a semiconductive material. Layers of materials are added, removed, and/or treated during fabrication to create the electrical circuits that make up the device. The fabrication essentially comprises four basic operations. The four operations are:                layering, or adding thin layers of various materials to a wafer from which a semiconductor is produced;        patterning, or removing selected portions of the added layers;        doping, or placing specific amounts of dopants in the wafer surface through openings in the added layers; and        heat treatment, or heating and cooling the materials to produce desired effects in the processed wafer.        
Although there are only four basic operations, they can be combined in hundreds of different ways, depending upon the particular fabrication process.
One technique for improving the operation of the semiconductor processing line includes using a factory wide control system to automatically control the operation of the various processing tools. The manufacturing tools communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface which facilitates communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script based upon a manufacturing model, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. Often, semiconductor devices are staged through multiple manufacturing tools for multiple processes, generating data relating to the quality of the processed semiconductor devices.
During the fabrication process various events may take place that affect the performance of the devices being fabricated. That is, variations in the fabrication process steps result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the device. Various tools in the processing line are controlled in accordance with performance models to reduce processing variation. Commonly controlled tools include photolithography steppers, polishing tools, etching tools, and deposition tools. Pre-processing and/or post-processing metrology data is supplied to process controllers for the tools. Operating recipe parameters, such as processing time, are calculated by the process controllers based on the performance model and the metrology information to attempt to achieve post-processing results as close to a target value as possible. Reducing variation in this manner leads to increased throughput, reduced cost, higher device performance, etc., all of which equate to increased profitability.
One commonly controlled process is the patterning operation, which is also sometimes called photolithography, photomasking, masking, and microlithography. The term “photolithography” will hereafter be used to refer to patterning operations. In photolithography, typically, a machine called a “stepper” positions a portion of a wafer being processed under a “reticle,” or photomask. A reticle is a pattern created in a layer of chrome on a glass plate. Light is then shone onto the wafer through the reticle. The chrome blocks some of the light. Other types of reticles use phase shifting features in conjunction with or in lieu of a chrome layer. The light shining through the pattern on the reticle changes the material characteristics of the layer of photoresist material formed on the wafer where it illuminates the layer of photoresist. These changes make the photoresist material more or less susceptible to removal in another operation, depending on the particular process being implemented. The stepper then positions another portion of the wafer under the reticle, and the operation is repeated. This process is repeated until the entire wafer has undergone the stepper exposure operation.
Next, portions of the photoresist layer are removed or developed to expose selected portions of the underlying process layer. Thereafter, typically through one or more etching processes, the exposed portions of the underlying process layer are removed to define a pattern in the underlying process layer. The purpose of photolithography is to define in a layer of photoresist what will ultimately become patterns in or on a process layer formed on the wafer, the parts of which may ultimately become parts of the semiconductor device. These patterns in the layer of photoresist must be laid down precisely in the exact dimensions, within certain manufacturing tolerances, required by the circuit design, and the patterns must be located in the proper place.
The photolithography operations generally set the “critical dimensions” of the semiconductor devices (e.g., the width of the gate conductor in an illustrative field effect transistor), which are referred to as final inspection critical dimensions (FICD). The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD). Errors in the photolithography process can cause a whole host of problems including, but not limited to, distorted patterns, misplaced patterns, and other defects. These types of errors can ultimately result in undesirable changes in the functioning of the electrical circuits so that the wafer has to be scrapped. Photolithography processes are performed at very small dimensions, so that they are also highly susceptible to contamination by unwanted variations in processing conditions.
To identify and control photolithography variations various metrology and automatic control techniques are employed. For example, post exposure metrology tests that employ scatterometry measurements or physical measurements may be conducted to determine the proper overlay and/or develop inspect critical dimensions of the photoresist layer. Based on the measured characteristics, a process controller may be employed to automatically adjust the parameters of the photolithography process (e.g., exposure dose, post exposure bake time, photoresist layer thickness, etc.) to reduce variation in the patterning process. If a measured characteristic of the photoresist layer is determined to be sufficiently outside tolerances, the photoresist layer is removed and the wafer is reworked to generate a new patterned layer.
Another fabrication process susceptible to rework is planarization, typically accomplished by a chemical mechanical polishing (CMP) operation. CMP is a widely used means of planarizing silicon dioxide as well as other types of process layers on semiconductor wafers. Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of a process layer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be disbursed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, the surface of the wafer is mechanically and chemically polished.
Various automatic control techniques are employed to reduce post-polish thickness variation. For example, post-polish metrology data may use used to develop a control model of the polishing tool to account for expected degradation due to the depletion of consumable polishing pads employed in the tool. Post-polish planarity measurements may also be used to identify a wafer that has not been adequately planarized. Such a wafer may be reworked to complete the planarization process.
Reworking wafers due to photolithography or planarization process errors is time consuming, requiring both additional tool time and operator time. Hence, the efficiency and profitability of the fabrication system are reduced.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.